FIG. 1 of the accompanying drawings illustrates a known type of switched capacitor digital/analog converter (DAC) for converting an n-bit digital word to a corresponding analog output. The DAC comprises n-capacitors C1, . . . , Cn with the capacitance Ci of each ith capacitor being equal to 2(i−1) C1. The DAC further comprises a terminating capacitor CTERM connected between the input of a unity gain buffer 1 and ground. The first electrodes of the capacitors C1, . . . , Cn are connected together and to the first terminal of the terminating capacitor CTERM. The second terminal of each of the capacitors C1, . . . , Cn is connected to a respective switch, such as 2, which selectively connects the second electrode to a first or second reference voltage input V1 or V2 in accordance with the state or value of a corresponding bit of the digital word. The output of the buffer 1 drives a capacitive load CLOAD, for example in the form of a data line or column electrode of an active matrix of a liquid crystal device.
The DAC has two phases of operation, namely a resetting or “zeroing” phase and a converting or “decoding” phase, controlled by internally generated timing signals which are not illustrated in FIG. 1. During the zeroing phase, the first and second electrodes of the capacitors C1, . . . , Cn and the first electrode of the terminating capacitor CTERM are connected together by an electronic switch 3 and to the first reference voltage input V1. The capacitors C1, . . . , Cn are therefore discharged so that the total charge stored in the DAC is equal to V1CTERM.
During the decoding phase, the second electrode of each capacitor Ci is connected to the first reference voltage input V1 or to the second reference voltage input V2 according to the value of the ith bit of the digital input word. The charge stored in the DAC is given by:
  Q  =                    ∑        i            ⁢                        b          i                ⁢                              C            i                    ⁡                      (                                          V                DAC                            -                              V                2                                      )                                +                  ∑        i            ⁢                        (                      1            -                          b              i                                )                ⁢                              C            i                    ⁡                      (                                          V                DAC                            -                              V                1                                      )                                +                  V        DAC            ⁢              C        TERM            where bi is the ith bit of the input digital word and VDAC is the voltage at the first electrodes of the capacitors C1, . . . , Cn and CTERM. The output voltage is therefore given by:
      V    DAC    =            V      OUT        =                                                      ∑              i                        ⁢                                          b                i                            ⁢                              C                i                                                                                        ∑                i                            ⁢                              C                i                                      +                          C              TERM                                      ⁢                  (                                    V              2                        -                          V              1                                )                    +              V        1            
In general, Ci=2(i−1) C1 and C1 =CTERM. This results in a set of output voltages which are linearly related to the input digital word.
In order to isolate the load capacitance from the DAC and to prevent it from affecting the conversion process, the unity gain buffer 1 is provided. However, such buffers are a substantial source of power consumption. If the buffer 1 were to be omitted, the terminating capacitance would be increased by the addition of the load capacitance so that the maximum output voltage from the DAC would be given by:
      V          OUT      ⁡              (        MAX        )              =                                          ∑            i                    ⁢                      C            i                                                              ∑              i                        ⁢                          C              i                                +                      C            TERM                    +                      C            LOAD                              ⁢              (                              V            2                    -                      V            1                          )              +          V      1      
The effect of this may be reduced by increasing the value of the switched capacitors. However, this increases the power consumption of and the area of an integrated circuit occupied by the DAC. In order to achieve voltages near to the higher reference voltage, such as that supplied to the reference voltage input V2, the capacitances must be increased substantially.
Another technique for compensating for this effect is to increase the higher reference voltage supplied to the input V2. However, this also increases the power consumption of the DAC and may also require more complex or powerful circuitry to generate the higher reference voltage.
In some applications, DACs are required to generate an output voltage as a non-linear function of the input digital word. For example, FIG. 2 illustrates the required transfer function when a DAC is used as part of a driving arrangement for a liquid crystal display and FIG. 3 of the accompanying drawing illustrates how such a transfer function is modified in order to provide gamma correction. GB2388725 discloses a non-linear DAC in which non-linearity is achieved by providing switched capacitors which are not binary-weighted. By using such an arrangement with a relatively large terminating capacitor, it is possible to connect the DAC directly to the load and without an intermediate buffer as illustrated in FIG. 4 of the accompanying drawings. However, the same limit on the maximum output voltage as described hereinbefore applies to such an arrangement. Further, such a DAC is restricted to providing transfer characteristics with rotational symmetry. For example, in the case of a 6-bit converter within input words or codes in the range of 0 to 63, Vb−V0=V63−Vb′, where b is a 6-bit digital code and b′ is the ones complement thereof as illustrated in FIG. 5 of the accompanying drawings. Thus, although a DAC of this type can approximate the curve illustrated in FIG. 2, in general it cannot adequately approximate non-symmetrical curves such as that illustrated in FIG. 3.